Modification of Power Series Expansion

Modification of military unit Series ExpansionThe available rules to compute the logarithm of a come using digital circuits can be take offd in 2 main groups. On the angiotensin converting enzyme hand, we have the look-up plank ground algorithmic ruleic rules and, on the other, iterative methods. The first approach is faster and straightforward, merely yet helpful for low precision. For giveing it, requires large amount of memory for increasing the accuracy. This is receivable to the coat of the look-up table. We only evaluated iterative algorithms that need small look-up tables. The second group is slower, but suitable for high precision. Taylors series intricacy is among the most popular methods to manually compute logarithms, but it has a slow convergence and requires slow trading operations like the division. Hence, they be slow when no embedded multipliers are available. galore(postnominal) studies explore hybrid implementations that take advantages from twain groups.Our project required an algorithm that could be implemented on FPGAs from any vendor. It should be platform independent. Our algorithm requires less memory and no multiplier at all to implement superpowerial and logarithm cultivate.To the best of our knowledge there are only dickens previous works focused on the exponentialfunction 8 9, and only one for the logarithm function 10 (from the same authors of 9).The first one 8, employs an algorithm that does not exploit the FPGA characteristics, andconsequently presents poor performance. The other two implementations 9, 10 are part ofa common work and are de firmed suiting with FPGA flexibility (using inhering tailored fixedarithmetic and exploiting the symmetry features of the FPGA) achieving much better results.They are parameterizable implementations that, additionally to single f.p. format, also throw overboardsmaller exponent and mantissa bit-widths and are both based on stimulation range decline andtable-driven methods to calculate the function in the trim down range. Our ex and ln x units,based on these units, include the following innovative featuresSingle precision f.p. arithmetic generation. 9, 10 were de sign-language(a) considering only normalized tallys, not denormalized. special logic has been introduced to handledenormalized numbers at the payoff of ex and the input signal of ln x. Redesign of units to deal only with single precision. The feature of bit-width config-urability of the base designs has been removed. Thus, the resources mandatory have beenreduced because specific units, just for single precision, have been developed. simplification of constant multiplications. As suggested in 9, conventional multipliershave been removed where the multiplications voluminous constant coecients, improvingperformance and reducing size. Unsigned arithmetic. In 9, 10 internal fixed arithmetic with sign is used. However,some operations (like the ones involving range reduction and c alculation of the exponentfor the result in ex) are consecutive and related, and the sign of the result can be inferredfrom the input sign. For such operations signed arithmetic has been replaced by unsignedarithmetic with the corresponding logic reduction. meliorate pipelining. The speed is enhanced by systematically introducing pipelinestages to the datapath of the exponential and logarithm units and their subunitsThe paper 11 explains about the implementation of power and log function based on a simple modification of power series expansion of Taylor series. In power function implementation, the paper aims at reducing the exponent number to a smaller value. It requires a large amount of pin ram and hardware multipliers as well. It becomes platform dependent and the clock relative frequency may vary from vendor to vendor. The degradation in throughput rate is due to the use of 18 X 18 embedded multipliers in it. The powering unit also requires more number of stages which may be reduced further.In the proposed method, we are going to reduce delay and improve the throughput rate by obviateing the embedded multipliers and block RAMs. In this paper, we are not completely avoid look up tables, but any value of logarithm or exponential can be calculated, by adjusting the look up table values to the desired number8 C. C. Doss and R. L. Riley, FPGA-Based implementation of a copious IEEE-754 ex-ponential unit, in IEEE Field-Programmable Custom Computing Machines, 2004, pp.229238.9 J. Detrey and F. de Dinechin, A parameterized oating-point exponential function forFPGAs, in IEEE International collection Field-Programmable Technology, 2005, pp.2734.10 , A parameterized oating-point logarithm operator for FPGAs, in Signals, Systems and Computers, 2005. Conference Record of the Thirty-Ninth Asilomar Conference,2005, pp. 11861190.11 Pedro Echeverra, Marisa Lopez-Vallejo,An FPGA Implementation of the Powering Function with Single Precision Floating-Point arithmeticAn FPGA Implementation of the Powering Function with Single Precision Floating-Point ArithmeticPROPOSED METHODThe proposed method avoids multiplication and division operations, and is thus suitable for implementation in software system on processors that lack such instructions (or where the instructions are slow) or in hardware on a programmable logic device or dedicated chip. This method is suitable when shifters are available in abundant. It is an extension to the implementation of sine and cosine explained in CORDIC. The proposed algorithm evaluates the power functions for both positive and cast out values. There are some constants by which it is well-fixed to multiply. For example, multiplying by 2n, where n is a positive or a negative integer, can be achieved by simply shifting a number by n places. The shift will be to the left (division) if n is positive, to the right (multiplication) if n is negative. It is nearly as easy to multiply by numbers of the form 2n1. These simply involve an add (or) infer a shift.Implementation of EXP For implementing y = exp(x). The algorithm is going to generate a time of values for x and y, and we are going to install sure that for all(prenominal) pairKExp(k)5.54522562.7726161.386340.693120.40553/20.22315/40.11789/80.060617/160.030833/320.015565/640.0078129/128y=exp(4)y=exp(4)exp(-(xk))=exp(4)exp(-x)exp(k)=yexp(k).In other words, if we subtractkfromx, we have to multiplyyby exp(k). All we have to do now is make sure that exp(k) is a beautiful number, so we can multiply by it easily, and the rest is straightforward. Note thatkitself does not have to be nice, as we are only subtracting that, not multiplying by it. Here are some nice values of exp(k) and the corresponding (not necessarily nice) values ofk.The flow of algorithm is as follows for positive powers of xHere in each iteration, we subtract the input from the nearest value of exp(k) as listed in the table. If the difference is negative, we multiply the output by the corresponding exp(k). The process continues withmore entities in our table of k, lastly we depress the result. In the same way the flow chart is mentioned for nagative powers of x.KExp(k)5.54522562.7726161.386340.693120.28773/40.13357/80.064515/160.031731/320.015763/640.0078127/1280.0039255/256The flow of algorithm is as follows for negative powers of xHere in each iteration, we subtract the input from the nearest value of exp(k) as listed in the table. If the difference is positive, we divide the output by the corresponding exp(k). The process continues withmore entities in our table of k, finally we get the result.Implementation of LOG For implementing Y=log (x), the procedure is quasi(prenominal) to the implementation of exponential function